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TE CH
T221160A
DRAM
FEATURES
64K x 16 DYNAMIC RAM
FAST PAGE MODE PIN ASSIGNMENT ( Top View )
V cc I/01 I/02 I/03 I/04 V cc I/05 I/06 I/07 I/08 NC NC WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 V ss I/016 I/015 I/014 I/013 V ss I/012 I/011 I/010 I/09 NC CASL CASH OE NC A7 A6 A5 A4 VSS
* High speed access time : 25/30/35/40 ns * Industry-standard x 16 pinouts and timing functions. * Single 5V (10%) power supply. * All device pins are TTL- compatible. * 256-cycle refresh in 4ms. * Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. * Conventional FAST PAGE MODE access cycle. * BYTE WRITE and BYTE READ access cycles.
SO J
31 30 29 28 27 26 25 24 23 22 21
PART NUMBER EXAMPLES
PART NUMBER
R AS NC A0 A1
ACCESS TIME 30ns 30ns 35ns 35ns
PACKAGE SOJ TSOP-II SOJ TSOP-II
T221160A-30J T221160A-30S T221160A-35J T221160A-35S
A2 A3 V cc
V cc I/01
1 2 3 4 5 6 7 8 9 10 T S O P (II)
40 39 38 37 36 35 34 33 32 31
V ss I/01 6 I/01 5 I/01 4 I/01 3 V ss I/01 2 I/01 1 I/01 0 I/09
GENERAL DESCRIPTION
The T221160A is a randomly accessed solid state memory containing 1,048,551 bits organized in a x16 configuration. The T221160A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode operation The T221160A CAS function and timing are
I/02 I/03 I/04 V cc I/05 I/06 I/07 I/08
NC
11 12 13 14 15 16 17 18 19 20
30 29 28 27 26 25 24 23 22 21
NC CA SL CA SH OE NC A7 A6 A5 A4 V SS
determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and CASH transiting low will write data into the upper byte (IO9~16). Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice.
NC WE RAS NC A0 A1 A2 A3 V cc
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
FUNCTIONAL BLOCK DIAGRAM
WE CASL CASH
CAS
CONTROL LOGIC
DATA-IN BUFFER DQ01 16
. .
DQ16
NO.2 CLOCK GENERATOR DATAOUT BUFFER 8 COLUM N. ADDRESS BUFFER 8 COLUM N DECODER
OE
16
A0 A1 A2 A3 A4 A5 A6 A7 8 REFRESH COUNTER REFRESH CONTROLLER
256 8 SENSE AM PLIFIERS VO GATING 256 x 16 8
ROW DECODER
8
ROW . ADDRESS BUFFERS(8)
8
256
256 x 256 x 16 M EM ORY ARRA Y
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
PIN DESCRIPTIONS
PIN NO. 16~19,22~25 14 28 29 13 27 2~5,6~10,31~34,36~39 1,6,20 21,35,40 11,12,15,30 SYM. A0-A7 RAS CASH CASL WE OE I/O1 - I/O16 Vcc Vss NC TYPE Input Input Input Input Input Input Address Input Row Address Strobe Column Address Strobe /Upper Byte Control Column Address Strobe /Lower Byte Control Write Enable Output Enable DESCRIPTION
Input/ Output Data Input/ Output Supply Ground Power, 5V Ground No Connect
Taiwan Memory Technology, Inc. reserves the right P. 2 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS... ... -1V to 7V Operating Temperature, Ta (ambient)..0C to +70C Storage Temperature (plastic)....... -55C to +150C Power Dissipation ........................................... 1.0W Short Circuit Output Current.......................... 50mA *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 5V 10 % unless otherwise noted) DESCRIPTION CONDITIONS Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V VIN 7V 0V VOUT 7V Output Leakage Current Output(s) disabled Output High Voltage IOH = -5 mA Output Low Voltage IOL = 4.2 mA Note: 1.All Voltages referenced to Vss SYM. Vcc Vss VIH VIL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 MAX 5.5 0 Vcc+1 0.8 10 10 0.4 UNITS V V V V uA uA V V NOTES 1 1 1
Taiwan Memory Technology, Inc. reserves the right P. 3 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
DC CHARACTERISTICS
(Ta = 0 to 70C, Vcc = 5V 10%, Vss = 0V)
Parameter Operating Current Standby Current Icc2 Standby Current Fast Page Mode Current RAS -only refresh Current CAS Before RAS Refresh Current 4 4 4 4
Symbol
-25
-30
-35
-40
Unit
Test Condition RAS , CAS cycling tRC=min TTL interface,
Min Max Min Max Min Max Min Max
Icc1
-
170
-
150
-
130
-
120 mA
mA RAS , CAS =VIH, DOUT=High-Z CMOS interface, RAS , CAS > Vcc-0.2V
Icc3 Icc4 Icc5 Icc6
-
2
-
2
-
2
-
2
mA
170 170 170
150 150 150
130 130 130
RAS =VIL, CAS 120 mA cycling, t = min PC CAS =VIH, RAS 120 mA cycling, t = min RC 120 mA RAS , CAS cycling, tRC= min
Note:
Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current.
CAPACITANCE
(Ta =25C, Vcc =5V, f = 1M HZ)
Parameter Input Capacitance (address) Input Capacitance ( RAS , CAS , WE , OE ) Output Capacitance (data-in/out) Symbol CI1 CI2 CI/O Typ Max 5 7 10 Unit pF pF pF
Taiwan Memory Technology, Inc. reserves the right P. 4 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
AC CHARACTERISTICS (note 1,2,3) (Ta = 0 to 70C)
AC TEST CONDITIONS: Vcc=5V 10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF)
AC CHARACTERISTICS PARAMETER Read or Write Cycle Time Read-Modify-Write Cycle Time Fast-Page-Mode Read or Write Cycle Time Fast-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge RAS Pulse Width RAS Pulse Width RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time Read Command Setup Time SYM tRC tRWC tPC tPCM tRAC tCAC tOAC tAA tACP tRAS -25 43 65 15 37 25 7 7 12 14 -30 55 85 20 42 30 8 8 16 18 -35 65 95 23 49 35 9 9 18 20 -40 75 105 25 52 40 10 10 20 22
UNIT Notes MIN MAX MIN MAX MIN MAX MIN MAX
ns ns ns ns ns 4 ns 5 ns 13 ns 8 ns
25 10K 30 10K 35 10K 40 10K ns tRASC 25 100K 30 100K 35 100K 40 100K ns ns tRSH 7 8 9 10 tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR 15 4 21 3 10 3 0 5 8 0 4 22 12 0 0 0 3 3 15 17 10K 20 6 26 3 10 3 0 5 8 0 4 26 14 0 0 0 3 3 15 21 10K 23 8 25 ns 10K 10 10K ns ns 30 35 ns 4 5 10 3 0 5 8 0 4 30 16 0 0 0 3 3 15 25 10 5 0 5 8 0 5 34 18 0 0 0 3 3 15 29 ns 7 ns ns ns ns 8 ns ns ns ns ns 14 ns 9,14 ns 9 ns ns 10,16
13
14
16
18
tRAL tRCS Read Command Hold Time Reference to CAS tRCH Read Command Hold Time Reference to RAS tRRH CAS to Output in Low-Z Output Buffer Turn-off Delay From CAS or RAS tCLZ tOFF1
Taiwan Memory Technology, Inc. reserves the right P. 5 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
-25 -30 -35 -40 SYM MIN MAX MIN MAX MIN MAX MIN MAX UNIT Notes tOFF2 tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tORD 10 5 7 4 0 0 4 22 4 5 5 0 4 22 34 21 17 1.5 50 4 10 10 10 4 0 6 0 4 26 4 6 6 0 4 26 46 29 24 1.5 50 4 10 10 10 4 0 8 0 4 30 4 7 7 0 4 30 51 31 25 2.5 50 4 10 10 10 5 0 8 0 6 34 6 9 8 0 5 34 56 35 27 2.5 50 4 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns
6 6 15 11 11 11 2,3 14 16 11,14
AC CHARACTERISTICS (continued)
AC CHARACTERISTICS PARAMETER Output Buffer Turn-off OE to Write Command Setup Time Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (256 cycles) RAS to CAS Precharge Time CAS Setup Time (CBR REFRESH) CAS Hold Time (CBR REFRESH) OE Hold Time From WE During ReadModify-Write Cycle OE Setup Prior to RAS During Hidden Refresh Cycle
14 14 14 12 12
Taiwan Memory Technology, Inc. reserves the right P. 6 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
T221160A
11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If tWCS tWCS(min), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min), tAWD tAWD(min) and tCWD tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE controlled) cycle. 12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. WRITE command is defined as WE going low. 15. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 16. The I/Os open during READ cycles once tOFF1 or tOFF2 occur.
Notes: 1. An initial pause of 200us is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH(2.4V) and VIL(0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that tRCD tRCD(max) . 6. Enables on-chip refresh and address counters. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
Taiwan Memory Technology, Inc. reserves the right P. 7 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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TE CH
READ CYCLE
t
T221160A
RC RAS
t
t
RP
VIH RAS VIL
t
t
t
CRP
t
CSH RSH
t t
CRP
t
RCD
RRH
VIH CAS VIL
t t
CAS
t
AR
t t
RAD RAH ASC
RAL
ASR
t
t
CAH
VIH ADDR VIL WE VIH VIL
ROW
t
COLUMN
RCS
t
ROW
RCH
t t t
AA
NOTE1
RAC CAC CLZ
VAILD DATA
t
OFF1
t
VIOH I/O VIOL VIH OE VIL
OPEN
OPEN
t
OAC
t
OFF2
EARLY WRITE CYCLE
tRC tRAS tRP
VIH RAS VIL
tCRP tRCD
tCSH tRSH tCAS tCRP
RAS
VIH VIL
t t
tAR
ASR
RAD t RAH
t t
RAL CSH
ASC
t
VIH ADDR VIL
ROW
COLUMN
tCWL tRWL t tWCS
ROW
WCR
tWCH tWP tDHR
VIH WE VIL
tDS
tDH
VIOH VIOL VIH OE VIL I/O
VAILD DATA
DON'T CARE
UNDEFINED
Note: tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right P. 8 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
tm
CAS
TE CH
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
T221160A
RWC RAS
t
t
RP
VIH RAS VIL
t
t
CSH
t
tRSH
CRP
t
RCD
t
CAS
CRP
VIH VIL
t tASR
t
AR
t tASC
RAD
RAL
tRAH
tCAH
VIH ADDR VIL
ROW
t
COLUMN
t
ROW
RWD CWD
t t
CWL RWL
tWP
RCS
t
tAWD
VIH WE VIL
t t t
AA
t
RAC CAC DS
t
DH
tCLZ
VIOH I/O VIOL
t
VAILD DOUT
VAILD D
IN
t
OAC
OFF2
t
OEH
VIH OE VIL
FAST-PAGE-MODE READ CYCLE
t
RA SC
t
RP
RAS
V V
IH IL
t t
CSH
t
t
PC
t
t
t
RSH
CRP
t
CRP
t
RCD
CAS
t
CP
CAS
t
CP
t
CAS
CPN
V CAS V
IH IL
t t t
AR
t t
RAD ASC
t
RAL
ASR
t
RAH
CAH
t
ASC
t
CAH
t
ASC
t
CAH
ADDR
V V
IH IL
ROW
COLUM N
COLUM N
COLUM N
t
ROW
RRH
t
RCS
t
RCH
WE
V V
IH IL
t t t t
t
AA
t t
t
AA
AA
t
ACP CAC
t
RAC CAC O FF1
t
V A IL D DATA
ACP CAC
t
t
O FF1
t
t
O FF1
CLZ
CLZ
V A IL D DATA OPEN
V I/O V
IO H
OPEN
CLZ
V A IL D DATA
IO L
t
OAC
t
O FF2
t
OAC
t
O FF2
t
OAC
t
O FF2
OE
V V
IH IL
D O N 'T C A R E
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of CAS . Both measurements must meet the tPC specification.
Taiwan Memory Technology, Inc. reserves the right P. 9 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
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VIH RAS VIL VIH CAS VIL
TE CH
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
T221160A
RASC
t
RP
t t
CSH
t
t
PC
t
t t t
t
RSH
t
CRP
t
CRP
t
RCD
CAS, CLCH
t
t
CP
CAS, CLCH
CP
t
CAS, CLCH
CPN
t tRAD t
AR
tRAL t
ASR
t
RAH
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
VIH ADDR VIL
ROW
COLUMN
t tWCS
COLUMN
t tWCS
COLUMN
t tWCS
ROW
CWL
CWL
CWL
tWCH t
tWCH t
tWCH t
WP
WP
WP
VIH WE VIL
t
t
WCR DHR
t
t
RWL
t
DS
DH
t
DS
t
DH
t
DS
t
DH
VIOH I/O VIOL VIH OE VIL
VALID DATA
VALID DATA
VALID DATA
FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
tRASC tRP
RAS VIH VIL
tCRP tRCD
tCSH tCAS,tCLCH tCP
tPCM tCAS,tCLCH tCP
tRSH tCAS,tCLCH
tCRP tCPN
CAS
VIH VIL
tASR
tAR
tRAD tRAH tASC tCAH tASC tCAH tASC tRAL tCAH
VIH ADDR VIL
ROW
COLUMN
tRWD tRCS tAWD tCWL tWP tCWD
COLUMN
tCWL tAWD tWP tCWD
COLUMN
ROW
tRWL tCWL tWP
tCWD
VIH WE VIL
tAA tRAC tCAC tCLZ tDH tDS tACP tCAC tCLZ
VAILD D OUT VAILD D IN VAILD D OUT VAILD D IN
tAA tDH tDS
tAA tDH tACP tCAC tCLZ
VAILD D OUT VAILD D IN
tDS
I/O
VIOH VIOL
tOAC
tOFF2 tOAC
tOFF2 tOAC
tOFF2 tOEH
OE
VIH VIL DON'T CARE UNDEFINED
Note: tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. Taiwan Memory Technology, Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date:FEB. 2002 Revision:A
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RAS V IH V IL CAS V IH V IL
TE CH
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE)
t
T221160A
RASC
t
RP
t t t
CSH
t t
t
PC
t t
CRP
RCD
CAS
CP
t
PC
CAS
t
CP
t RSH t CAS
CRP
t
CP
t t t
AR
t t
RAD A SC
t
RAL
A SR
t
RAH
CAH
t
A SC
t
CAH
t
A SC
t
CAH
ADDR
V IH V IL
ROW
COLUM N
COLUM N
t
COLUM N
ROW
RCH
t
t
RCS
WCS
t
WCH
WE
V IH V IL
t
t t
AA
AA
t t
ACP
t
RAC
t
CAC CLZ
t
CAC
O FF1
t
t
DS
t
DH
O FF1
V A IL D D A T A IN
I /O
V IO H V IO L V IH V IL
OPE N
V A IL D D A T A (A )
V A IL D D A T A (B )
t
OAC
OE
RAS ONLY REFRESH CYCLE (ADDR=A0-A7 ; OE , WE =DON`T CARE)
t tRAS
RC
tRP
VIH RAS VIL
tCRP tRPC
CAS
VIH VIL
tASR tRAH
VIH ADDR VIL
ROW
ROW
tOFF
I/O
VOH VOL
OPEN
DON'T CARE UNDEFINED
Note1:Do not drive data prior to tristate.
Taiwan Memory Technology, Inc. reserves the right P. 11 to change products or specifications without notice.
Publication Date:FEB. 2002 Revision:A
tm
TE CH
CBR REFRESH CYCLE (A0-A7 ; OE =DON`T CARE)
t RC t
T221160A
RP
t RAS
t RP
t RAS
RAS
VIH VIL
tRPC tCPN tCSR tCHR tRPC tCSR tCHR
CAS
VIH VIL
tOFF
I/O
OPEN
WE
VIH VIL
HIDDEN REFRESH CYCLE ( WE =HIGH ; OE =LOW)
(R E A D )
t t
(R E F R E S H )
t t
RC RP
t
RC
t
RAS
RAS
RP
RAS
V V
IH IL
t
CRP
t
RCD
t
RSH
t
CHR
CAS
V V
IH IL
t t t
AR
t t
RAD ASC
t
RAL
ASR
t
RAH
CAH
ADDR
V V
IH IL
ROW
COLUM N
t t
AA
NOTE1
RAC
t
t
CAC
O FF1
V I/O V
t
IO H
O PEN
CLZ
V A IL D
t
DATA
O PEN
IO L
OAC
t
O FF2
OE
V V
t
IH IL
ORD
D O N 'T C A R E
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. Taiwan Memory Technology, Inc. reserves the right P. 12 to change products or specifications without notice. Publication Date: FEB. 2002 Revision:A
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40
TE CH
T221160A
PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil)
A
21
B
1
20
G K L I D C F
Seating Plane
H
y
E
10X(MAX )
J
SYMBOL A B C D E F G H I J K L y
DIMENSIONS IN INCHES 1.0250.010 0.4000.005 0.045(MAX) 0.0500.006 0.0190.003 0.0260.003 0.4400.010 0.0110.003 0.025(MIN) 0.3640.020 0.0470.006 0.150(MAX) 0.004(MAX)
DIMENSIONS IN MM 26.0350.254 10.1600.127 1.143(MAX) 1.270.152 0.4830.08 0.6610.080 11.1760.254 0.2800.080 0.635(MIN) 9.2460.508 1.1940.152 3.810(MAX) 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A
tm
TE CH
T221160A
PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil)
D
40 21
E E1
1
20
e
b
A
A2 y S E A T IN G P L A N E
A1
L L1
SYMBOL A A1 A2 b e D E E1 L1 L y
DIMENSIONS IN INCHES 0.047(max) 0.0040.002 0.0390.002 0.014(typ.) 0.0315(typ.) 0.7250.004 0.4630.008 0.4000.004 0.031 0.0200.004 0.004(max) 0~5
DIMENSIONS IN MM 1.20(max) 0.100.05 1.000.05 0.35(typ.) 0.80typ.) 18.410.10 11.760.20 10.160.10 0.80 0.5000.10 0.10(max) 0~5
Taiwan Memory Technology, Inc. reserves the right P. 14 to change products or specifications without notice.
Publication Date: FEB. 2002 Revision:A

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